1. Technical Field of the Present Invention
The present invention generally relates to electrostatic discharge circuits, and more specifically, to electrostatic discharge power clamp circuits.
2. Background of the Present Invention
Electrostatic Discharge (ESD) events, which can occur both during and after manufacturing of the Integrated Circuit (IC), can cause substantial damage to the IC. ESD events have become particularly troublesome for CMOS and BiCMOS chips because of their low power requirements and extreme sensitivity.
A significant factor contributing to this sensitivity to ESD is that the transistors of the circuits are formed from small regions of N-type materials, P-type materials, and thin gate oxides. When a transistor is exposed to an ESD event, the charge applied may cause an extremely high current flow to occur within the device which can, in turn cause permanent damage to the junctions, neighboring gate oxides, interconnects and/or other physical structures.
Because of this potential damage, on chip ESD protection circuits for CMOS and BiCMOS chips is essential. In general, such protection circuits require a high failure threshold, a small layout size and a low Resistive/Capacitive (RC) delay so as to allow high speed applications.
An ESD event within an IC can be caused by a static discharge occurring at one of the power lines or rails. In an effort to guard the circuit against damage from the static discharge, circuits referred to as ESD clamps are used. An effective ESD clamp will maintain the voltage at the power line to a value which is know to be safe for the operating circuits, and not interfere with the operating circuits under normal operating conditions.
An ESD clamp circuit is typically constructed between a positive power supply (e.g.VDD) and a ground plane, or a ground plane and a negative power supply (VSS). The main purpose of the ESD clamp is to reduce the impedance between the rails VDD and VSS so as to reduce the impedance between the input pad and the VSS rail (i.e. discharge of current between the input to VSS), and to protect the power rails themselves from ESD events.
The never ending demand by the consumer for increased speed in Radio Frequency (RF) devices has resulted in some unique challenges for providing ESD protection in these high speed applications. More specifically, the physical size (e.g. Breakdown voltage) and loading effects of the ESD devices must now be considered in such high speed applications (e.g. 1-200 Giga Hertz range). The capacitive loading of the ESD device itself becomes a major concern for chips running at high frequencies, since the capacitive loading has an adverse effect on performance. For example, the capacitive loading effect of a typical ESD clamp at a frequency of 1 Hz is 0.5 pF, 10 GHz-0.1 pF, and at 100 GHz-0.05pF, 200 Ghz-0.01 pF).
It would, therefore, be a distinct advantage to have an ESD clamp that could provide substantial benefits in high speed devices while limiting any performance degradation from capacitive loading. The present invention provides such an ESD clamp.
The present invention is an ESD device that is useful in high speed radio frequency applications where size and loading effects are a concern. The ESD device is preferably constructed on a SiGe or equivalent type material that nearly approximates the Johnson Limit curve, and constructed in a Darlington type configuration. In the preferred embodiment of the present invention, the trigger device has a collector-to-emitter breakdown voltage (BVCEO) that is lower than that a frequency cutoff that is higher than that of the clamping device.